Digital Signal Processing Reference
In-Depth Information
equipment and other parts can all be in place before the test card arrives in the
laboratory.
4.2.2 Margining Power Supply
With the proper laboratory equipment, the power supply to the chip can be varied
(margined) to see how low or high the voltage can be set before the chip begins to
malfunction. Margining can also be used to determine which circuits are the first
to fail. This technique is especially powerful when the temperature of the air sur-
rounding the integrated circuit is simultaneously margined. As shown in Chapter
2, in general, low voltage and high temperature represent the extreme slow case
for CMOS integrated circuits, while low temperature and high voltage generally
represent the fast operation, high-current draw case.
4.2.3 Testing Decoupling Capacitor Effi cacy
The frequency content of the current drawn by an integrated circuit or a group of
chips under various switching and operating conditions can be determined by mea-
suring the current and performing a Fourier analysis on the waveform to obtain the
frequency spectra. Many modern oscilloscopes will directly perform a fast Fourier
transform (FFT), or the readings can be saved and externally processed by math-
ematical CAD programs such as MathCAD [1] or MATLAB [2].
By observing the spectra under various conditions, including with various I/O
switching patterns, the signal integrity engineer can determine the frequencies over
which the power supply decoupling network is operating. Specific frequencies with
particularly high amplitudes can be identified, and if necessary, decoupling can be
specifically designed to eliminate them.
4.2.4 Testing Sensitivity to Clock Quality
The chips sensitivity to clock amplitude, frequency, duty cycle and jitter can be
tested by replacing the expected clock source (often a crystal oscillator or PLL/
fanout circuit) with a laboratory function generator or test set. In this way the
sensitivity of the chip to clock quality, especially when tested over extremes of tem-
perature and power supply voltage, can be determined.
4.3 Evaluation Boards
Ideally, the test board used for debug can be given to prospective customers for
them to evaluate the operation of the ASIC, but in practice it is usually better to
have a different board for this purpose. In the past, the strategy of creating a single
test and evaluation board made economic sense when circuit board artwork could
only be created by layout specialists and when fabricating and assembly shops were
reluctant to take on small sized orders.
While it is true that the routing of high-speed, high-performance circuit boards
is best left to experienced specialists, the proliferation of layout design CAD tools
(some of which include auto routing software that is driven from the schematic to
