Digital Signal Processing Reference
In-Depth Information
Validate circuit models of various routing topologies, and to decide between
them.
•
Determine if a given trace width has adequately low loss and compare to the
simulation.
•
Determine crosstalk of critical routes, especially in dual stripline situations
that are difficult to simulate properly.
•
Validate I/O cell circuit models.
•
Determine the ability of a manufacturer to meet impedance specifications.
•
Determine the characteristics of traces routed near the board edge or other
cutouts in the board.
•
However, it is important for these boards not to become too intricate, espe-
cially if the experiments require excessive support from others. For instance, a dual
stripline crosstalk test would require that many lines be driven and some number
of them monitored. Support from other engineers will be required unless the signal
integrity engineer can design the logic or create the firmware necessary to do this.
In fact, it is critical not to lose sight that test boards are intended to reduce risk and
not to create it by siphoning off engineering resources that might be better used in
the development of the actual product.
4.2.1 Test Boards as a Chip Debug Platform
An important use of test boards is as a platform to facilitate the test and debug of
a new ASIC. For instance, a fabless semiconductor company would create such a
board so their engineers can validate and demonstrate the features of their chip in
an electrically controlled environment. This can be particularly helpful when pro-
viding customer support if the applications engineer can configure the ASIC in the
same way as the customer and demonstrate the same problem.
A test board is an important engineering tool because it is far less costly to de-
bug a new chip design on a test card than it is on the manufacturer's automatic test
equipment (ATE). Although deep, high-quality test patterns running on ATE are
critical for the manufacturer to determine if the ASIC works the way the designers
had intended, tracking an elusive bug on the ATE is inefficient and costly.
Instead, a test board can be developed that provides an electrically sound en-
vironment for the ASIC that includes jumpers, LEDS, test points, and connectors
that allow the designer to configure and test the chip under normal and extreme
conditions.
Test boards often have connections to visibility points that allow the designer
to observe or set logic deep within the ASIC. This is particularly helpful when the
chip can be placed in one or more test modes. Such modes are often not intended
for customer use and frequently redefine the normal function of ASIC I/O pins.
With a properly designed test card, the designer can use these pins in a test mode
without interference from the logic to which they would normally be connected.
A well-coordinated debug strategy includes a test plan that describes how to
use the test card with whatever test logic has been designed into the chip. In this
way test patterns can be written and any special fixtures or long lead time test
