Digital Signal Processing Reference
In-Depth Information
Circuit board vendors do not specify the manufacturing tolerances of the trace
widths or thicknesses, but on those traces specified as controlled impedance they
do indicate the impedance tolerance. This range is used by the SI engineer in simu-
lations to determine the optimum value of termination resistors and to find the
highest ringback and overshoot voltages.
2.4.1 Silicon Worst-Case I/O Models
Generally silicon vendors bound the range over which their device will operate by
providing nominal, fast (sometimes called best-case), and slow (sometimes called
worst-case) I/O circuit models. Because I/O driver performance is strongly depen-
dent on the die temperature (the junction temperature) and the actual power supply
voltage, these external factors must be appropriately set along with the proper I/O
case for a specific type of analysis. For example, CMOS I/O launches the slowest
signal rise time when the lowest power supply voltage and highest temperature is
used with the slowest case I/O model. To determine the highest current draw the
fast I/O model is used with a low die temperature, highest power supply voltage and
lowest transmission line impedance.
The temperature parameter used in the I/O models represents the junction tem-
perature, not the temperature of the ambient air. Sometimes this distinction can be
overlooked when the integrated circuit is a low power device, but it becomes criti-
cal as the device power dissipation increases. For instance, a commercial product
may operate in an ambient air temperature of 85°C or less. The junction tempera-
ture will not be much higher than this if the integrated circuit is low power device,
but (depending on the packaging) under the same circumstances the junction tem-
perature of a higher power device may exceed 125°C. The junction temperature is
estimated during prelayout and this value is used in the evolving SI model.
Although the junction temperature can be set in the simulation, not all CAD
tools have the ability to individually set the junction temperatures of various in-
tegrated circuits simultaneously coexisting in a simulation. When this is the case,
a net containing a device operating at a high junction temperature connected to a
device with a lower junction temperature will be simulated at one temperature (of-
ten the highest one). The result is that
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noise (noise on the power supply) and the
rise time of the signals launched by the I/O drivers will be underestimated for the
device operating at the lower temperature. This can mask signal integrity problems
such as the magnitude of overshoots and reflections.
2.4.2 What Combination of Environmental Effects Are Worst Case?
The precise combination of environmental conditions and circuit models that pro-
duce a particular worst-case condition depends on the details of a design, and some-
times the combination can be counterintuitive.
Rather than manually running through the various permutations, many SI
CAD tools can be set up to vary the parameters automatically and summarize the
results. This can be very helpful when designing large and complex circuit boards,
but adequate time should be included in the schedule to interpret and react to the
results.
