Digital Signal Processing Reference
In-Depth Information
operation. Some CAD tools support postlayout analysis, so if properly set up dur-
ing prelayout, the completed layout database can quickly be automatically ana-
lyzed for compliance and timing. Although this provides an enormous time savings,
especially on large multilayer boards, these tools are no substitute for a detailed
visual inspection of the artwork (and the SI engineer should always insist on having
enough time in the schedule to do this). The layout designer changes those things
identified by the CAD and visual inspections, and the SI engineer reexamines the
artwork. This process continues until the board fully meets the SI and timing re-
quirements for the product.
The layout designer formally releases the board to manufacturing once the
artwork has been corrected. The SI engineer uses this time to finish up any final
simulations and to finalize preparations for design verification testing (DVT).
Generally, DVT is carried out by the engineer responsible for the circuit board,
and not the SI engineer. Margin testing where voltage and temperatures are set to
extreme values is preformed during this phase, and bugs are uncovered. Test pat-
terns are used to exercise those highest risk nets identified during the prelayout and
layout phases. Often this phase is not distinct from debug, but some large firms
segregate these tasks and have different specialists for each. As described here, the
DVT process includes industry compliance testing, where those signals that must
strictly adhere to industry specifications are checked. In some cases, a third-party
testing laboratory is used to certify compliance.
Many SI engineers are not directly involved with laboratory debug. Instead,
they provide debug support by analyzing measurements taken by others and in
identifying critical test patterns and nets. This is especially likely if the SI engineer
is a CAD specialist and not one comfortable performing laboratory measurements.
However, the most valuable SI engineer is skilled in both CAD and measurement
techniques. These engineers have practical experience that is invaluable when inter-
preting simulation and measurement results.
The system is formally released to production for volume manufacturing once
the product has successfully passed through DVT and debug. Generally the SI en-
gineer is not involved in solving production problems, but they may be required to
help resolve timing or signal quality problems that arise during volume production
and are often required to help with component selection or evaluation when criti-
cal parts become unavailable. This is especially so if the SI engineer has laboratory
measurement experience, but SI CAD specialists are also enlisted. If properly docu-
mented and archived, the prelayout and postlayout design analysis (particularly
test patterns and environmental setup assumptions) can be immensely helpful in
solving urgent, unexpected production SI problems.
2.4
Signal Integrity Worst-Case Analysis
Often the SI simulations performed during the architectural phase are done under
nominal conditions. Circuit models for typical silicon are used, and traces, power
supply voltages, and termination resistor values are all assumed to be exactly as
specified. As the design progresses, the analysis progressively takes into account
process variations in the components, power supplies, and circuit board traces.
