Digital Signal Processing Reference
In-Depth Information
Ensure that the signal reference planes also connect to the I/O drivers (do not
use an unrelated voltage plane as a reference).
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Ensure that adequate decoupling is placed between power and ground planes.
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If a Thevenin termination is used, ensure that the Thevenin voltage is stable.
It must not oscillate and should have little droop even when many signals
connected to it simultaneously switch.
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16.4
Reducing and Eliminating Simultaneous Switching Noise (SSN)
Eliminating SSN from a poorly designed circuit board can be difficult and, in some
cases, impossible. It is best to analyze SSN effects before prototype hardware is fab-
ricated, especially that of the micropackage and any connectors (including sockets).
The following circuit board fixes can be helpful when an integrated circuit
experiences high SSN in those cases where little or no SSN analysis has been done.
This list is also useful during debug to help identify SSN.
Use power and ground planes to connect the ASIC to the power supply.
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Provide adequate decoupling capacitance adjacent to the IC pins. This is
extremely critical.
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Reduce the number of pins that simultaneously switch.
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Arrange for some signals to always switch in the opposite direction (odd-
mode parity, for instance) or stagger the timing so that some signals switch
later than others.
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Use differential signaling.
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Use a less powerful (lower current drive) I/O cell.
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In CMOS systems decrease the power supply voltage and increase the junc-
tion temperature. This will reduce SSN but will also adversely affect timing.
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Increase the transmission line impedance, since this reduces the launched
current.
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Use series termination on the circuit board since this reduces the launched
current.
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16.5
Improving Inadequate Timing Margins
Assuming that the root cause for the poor timing margin is signal integrity related
and that it does not involve poor logic design, one or more of the following circuit
board fixes can be helpful:
Guarantee that ringback and reflections are not eroding setup or hold times.
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Use a higher current drive I/O cell, remove series termination, and provide
parallel termination at the load (but these may increase crosstalk and simul-
taneous switching noise).
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