Digital Signal Processing Reference
In-Depth Information
from a manufacturing standpoint, but may not provide the best electrical
behavior.
Large antipads can remove extensive metal from the power or ground
plane, especially in dense pin fields such as under BGAs. This can result in
routing and (with high-power devices) power distribution problems.
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How was the trace impedance value selected for each layer?
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Has an analysis been done trading off ASIC driver strength and termina-
tion strategies and trace impedance?
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Lower-impedance traces result in a thinner overall stackup and make the
signals more immune to crosstalk, but increase driver current.
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Higher-impedance traces require less drive current and are more immune
to conductor loss but more sensitive to dielectric losses.
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How was the trace width arrived at for each signal or signal class?
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Often the minimum trace width allowed by the manufacturer is chosen
first, before any signal analysis is performed, but in some circumstances
a wider width is preferable. For instance, widening the trace reduces con-
ductor loss, and the crossover frequency where the dielectric loss becomes
larger than the conductor loss will change.
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Wider traces are easier to manufacture and generally result in less scrap
(lowering costs).
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Wide traces have lower inductance and larger capacitance than nar-
row ones. This is advantageous when routing power to terminators, for
example.
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A trace that is too narrow will limit the number of second sources capable
of manufacturing the board in volume.
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Narrow traces often have more variability in shape (and therefore imped-
ance and resistance) than do wide traces.
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How was the minimum trace spacing determined?
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Have crosstalk simulations (see Section 15.3) been performed that demon-
strate proper operation with the selected spacing?
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Spacing that is too small will limit the number of second sources capable
of manufacturing the board in volume.
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15.3
Questions to Ask When Reviewing Crosstalk Simulations
Does the I/O model produce the fastest signal rise time?
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The fast (sometimes called “best”) process corner produces the fastest rise
time.
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CMOS drivers produce the fastest rise time when the lowest permitted
temperature and highest permitted voltage are used with the fast transis-
tor models.
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Does the circuit board trace model include both conductor and dielectric
losses?
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Has the termination resistance and voltage been set to the worst case?
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