Digital Signal Processing Reference
In-Depth Information
formed showing this technique is cost effective compared to discrete
capacitors?
Are the cores so thin that the number of shops capable of fabricating the
board is limited and thus jeopardizing second source opportunities?
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Is an advanced laminate system being specified?
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If so, do the signal integrity simulations show an improvement in overall
board thickness, signal loss, crosstalk, or signal routing density significant
enough to warrant the added cost? If not, why isn't FR4 (or an enhanced
FR4 system) used?
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Can the chosen laminate be used by multiple fabrication shops to manu-
facture the circuit board? If not, do the electrical benefits outweigh the risk
of limited second sourcing?
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Does the stackup include many power planes?
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If so, can power planes be removed from the stackup (reducing cost and
overall thickness) and can components be rearranged to allow one or more
planes to be split and shared between more than one voltage?
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Are the most critical signals segregated to a specific signaling layer (or layers)?
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Often routing density and stackup improvements can be had by routing
the majority of critical (often impedance controlled) signals on specially
designed layers. This also allows the signal return paths to be carefully
designed.
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Are dual stripline layers used to maximum benefit?
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This can be an effective way of adding routing layers with only slight in-
crease to the stackup thickness.
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Coupling between layers is minimized when signals on alternate layers are
run at right angles to one another (for instance, north-south on one layer
and east-west on the adjacent layer).
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Careful signal integrity analysis is required to determine the amount of
crosstalk a bus will experience.
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Are the proper voltage planes used to form stripline and microstrip?
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A voltage plane unrelated to the signaling voltage must be carefully ana-
lyzed and modeled. Otherwise, the actual circuit will experience noise not
predicted by simulation.
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Are mounting holes located in a critical routing area?
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If so, verify that signaling has not been impaired by routing too close to the
hole or to a metallic screw.
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Are sharp rise time or critical signals routed close the board edge?
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If so, these signals may experience increased jitter and poor impedance
control, and the board may have increased EMI.
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What is the via/antipad strategy?
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Has the layout designer been allowed to select the via and antipad sizes,
or have these been designed? Often the layout designer selects the via
size based on layout and routing considerations. These may be optimum
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