Digital Signal Processing Reference
In-Depth Information
3.5V
3.0V
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
10 ns
15 ns
20 ns
25 ns
10 ns
15 ns
20 ns
25 ns
(a) (b)
Figure 12.10
Series-terminated clock waveform at the end of the 3-inch (7.6-cm) trace (a) when
all traces are the same length and (b) when the trace lengths differ (plotted with the same vertical
scale).
Figure 12.10(a) shows the waveform at load capacitor
C
L
3
when traces
T
1,
T
2,
and
T
3 are all 3 inches (7.6 cm) in length. The rising and falling edges transition
smoothly, without kinks (the signal is monotonic), and then high- and low-going
overshoot is well controlled.
In contrast, Figure 12.10(b) shows the voltage at
C
L
3
when transmission line
T
1 is 1 inch (2.5 cm),
T
2 is 2 inches (5.1 cm), and
T
3 is 3 inches (7.6 cm) in length.
The effect on the load of the unequal arrival time of the pulses at the near end
is evident. This waveform is not acceptable for a clock. The falling edge glitches
up to over 0.75V, and the negative-going overshoot is pronounced. To correct this
waveform, the traces should all be length matched, as shown in Figure 12.10(a), or
a clock fan-out device, a specialty integrated circuit made to distribute low skew
copies of an input signal, could be used.
12.7 Multidrop Lines
As shown schematically in Figure 12.11, rather than using point to point connec-
tions, a multidrop connection can be used to send a signal from a driver to multiple
loads.
The three load capacitors
C
L
1
through
C
L
3
are connected to the driver by tap-
ing into a transmission line. Each of these lines may be very long compared to the
signal rise time, or (more commonly) their electrical length may be comparable to
the rise time. Without proper termination and attention to length matching, signals
on multidrop lines are particularly likely to be nonmonotonic and to experience
multiple reflections.
