Digital Signal Processing Reference
In-Depth Information
to charge to the bias level. For this reason using AC termination on data buses re-
sults in significant data-dependent jitter [4] and is usually avoided.
Simple equations exist to calculate
C
term
from the signal rise time [5, 6], but
these are misleading because they underestimate the capacitance needed for fast
rise time, low-frequency signals. Equation (12.4) avoids this by providing an esti-
mate based on the signal frequency.
3
C
=
(12.4)
term
fZ
×
o
The equation computes the capacitance with a reactance 1/20th of
Z
o
at the
frequency
f
. The capacitor reaches its steady state bias level within 15 back-to-back
transitions. By that time the circuit is properly terminating the signal, but pulses
arriving before this time may not be.
For instance,
C
term
is 60 nF when
Z
o
is 50
and
f
is a 1-MHz clock. The ca-
pacitor has reached the steady state bias point by the 15th clock pulse (15
Ω
s).
The calculated value should be used as a starting point when performing circuit
simulations of the termination. The simulations ought to include the interconnect
parasitics (such as the via inductance) that are in series with the RC network since
these increase with frequency, diminishing the ability of
C
term
to act as an effective
connection for
R
term
.
Discrete resistors and capacitors are usually used to create the AC terminator,
but integrated RC networks are also available. As demonstrated in the Problems,
the capacitance of these networks is small, which makes them most useful in termi-
nating clocks with frequencies in the hundreds of megahertz range.
μ
12.6 Topologies
In Figure 12.7 the wiring between surface mount integrated circuits U1 and U4 is a
single load point to point connection, while the connection from U2 to U3, U5, and
U6 is an example of point-to-point multiload topology. The connection between
integrated circuits U7 through U10 is a multidrop topology.
These topologies have different electrical characteristics and, as we will see,
different response to various types of termination.
12.6.1 Single-Load Point-to-Point Termination
The series and parallel termination of a point-to-point single-load connection is
shown in Figure 12.8.
The series termination illustrated in Figure 12.8(a) shows a long transmission
line
T
2 connecting a capacitive load
C
L
to a series terminating resistor
R
s
. Ide-
ally,
R
s
is connected directly to the driver, but in general practice a length of trace
(shown as transmission line
T
1) is used to make the connection. This pin escape
trace is necessary because the physical size of
R
s
usually makes placing it immedi-
ately next to the driver pin impossible. This is especially true with large, fine-pitch
multipin ASICs where the pins (or balls if in a BGA package) are arrayed in several
