Digital Signal Processing Reference
In-Depth Information
A load line analysis can be performed to determine how the diodes on resis-
tance affects the clamped voltage, but the effects are seen best with a circuit simu-
lator. The simulations should include diode models from different manufacturers
because even for the same part number the circuit models often have different
characteristics. Therefore, simulations must show that the clamping is acceptable
with models from all the vendors supplying diodes for the build.
Although individual diodes can be used, dual diodes in three lead surface
mount packages specifically made for signal clipping are available that include
D
1 and
D
2 with a common connection between them. The common lead con-
nects to the signal trace and the other two leads connect to
V
dd
and ground. Some
examples of small signal silicon dual diodes in surface mount packages include the
MMBD1703, BAV99, MMBD4148SE, and the BAS40-04 (Schottky).
As part of the diode selection process, the circuit simulations should include
the measurement of the current through diode. The signal integrity engineer must
ensure that the clamping current is well within the diode current rating under all
switching conditions and environmental extremes.
12.5 AC Termination
The scheme shown in Figure 12.6 places a capacitor in series with the termination
resistor. This blocks the DC path so the network only dissipates AC power.
The acceptable value of blocking capacitor
C
term
falls within a wide range. The
general requirement is for the capacitors reactance to be very much smaller than
the resistance of
R
term
. In this way the capacitor acts as an AC short, connecting
R
term
directly to
V
term
(such as to ground, as is shown in the figure). However, if it
is made too large, excessive time is required to establish the proper bias across the
capacitor, adversely affecting the received signal amplitude.
This termination is best used with clocks or other repetitive signals, and is usu-
ally not suited for data buses or address lines where the frequency content of the
data stream varies. Very low frequencies corresponding to the back-to-back trans-
mission of many same sense bits require a large capacitor, but such a large value is
not appropriate when the signal frequency is high (corresponding to an alternating
1/0 pattern, for instance) because of the prolonged time required for the capacitor
V
dd
Z
o
V
V
ne
fe
TX
RX
R =
Z
o
term
C
term
V
tt
Figure 12.6
With AC termination TX only dissipates AC power.
C
term
's reactance is much less than
R
term
.
