Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 38

A-drv.

Module 128-256 F/Fs

B-drv.

Clock
Gen.

D-drvs. F/Fs with CCP

C-drv.

Leaf

Clock
Control
Registers

GCKD

GCKD

Hardware
(dynamic)

Software
(static)

Hardware (dynamic)

CCP: Control Clock Pin
GCKD: Gated Clock Driver Cell

ph1 edge trigger F/F ph2 transparent latch

Fig. 3.13 Clock-gating method of SH-X

Fig. 3.14 Pointer-controlled pipeline F/Fs of SH-X

E1

FF

E2

FF

E3

FF

E4

Register file

E5

Fig. 3.15 Conventional pipeline F/Fs

to reduce the activity ratio of the F/Fs. To address this issue, a pointer-controlled
pipeline was developed. It realizes a pseudopipeline operation with a pointer control.
As shown in Fig. 3.14 , three pipeline F/Fs are connected in parallel, and the pointer
is used to show which F/Fs correspond to which stages. Then, only one set of F/Fs
is updated in the pointer-controlled pipeline, while all pipeline F/Fs are updated
every cycle in the conventional pipeline as shown in Fig. 3.15 .
Table 3.6 shows the relationship between F/Fs FF0-FF2 and pipeline stages E2-E4
for each pointer value. For example, when the pointer indexes zero, the FF0 holds an
input value at E2 and keeps it for three cycles as E2, E3, and E4 latches until the