Heterogeneous Multicore Architecture - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 12

Fig. 2.2 Structures of
various local memories

a b c

PU PU PU

LM 1 LM i LM d LM i LM d

LM 2 LM 2

Hierarchical -
Harvard

Hierarchical Harvard

FVC

FVC FVC

SPP #0 SPP #n

CPU #0 CPU #m

PU PU PU PU

LM DTU LM DTU LM LM

On-chip bus (left) On-chip bus (right)

CSM l CSM r DMAC

Off-chip
main memory

Fig. 2.3 Example of other heterogeneous multicore con fi gurations

In Fig. 2.3 , we can see other configurations of a DTU, CSM, FVC, and an on-chip
interconnect. First, processor cores are divided into two clusters. The CPU cores,
the CSM l , and the off-chip main memory are tightly connected in the left cluster.
The SPP cores, CSM r , and the DMAC are nearly connected in the right cluster.
Not every SPP core has a DTU inside. Instead, the DMAC that has multiple chan-
nels is commonly used for data transfer between an LM and a memory outside an
SPP core. For example, when data are transferred from an LM to the CSM r , the
DMAC reads data in the LM via the right on-chip bus, and the data are written on
the CSM r from the DMAC. We need two bus transactions for this data transfer. On
the other hand, if a DTU in a CPU core on the left cluster is used for the same
transfer, data are read from an LM by the DTU in the core, and the data are written
on the CSM l via the on-chip bus by the DTU. Only one transaction on the on-chip
bus is necessary in this case, and the data transfer is more efficient compared with
the case using the off-core DMAC. Although each CPU core in the left cluster has
an individual FVC, the SPP cores in the right cluster share an FVC. With this simpler
FVC configuration, all SPP cores operate at the same voltage and the same fre-
quency, which are controlled simultaneously.