Heterogeneous Multicore Architecture - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 11

Chip

FVC FVC FVC FVC

CPU #0 CPU #m SPP a #0 SPP a #n

PU PU PU PU

LM DTU LM DTU LM DTU LM DTU

On-chip interconnect

SPP b #0 SPP b #k

On-chip
shared memory
(CSM)

PU PU

Off-chip
main memory

LM DTU LM DTU

FVC FVC

Fig. 2.1 Heterogeneous multicore architecture

command chaining, where multiple commands are executed in order. The frequency
and voltage controller (FVC) connected to each core controls the frequency, voltage,
and power supply of each core independently and reduces the total power con-
sumption of the chip. If the frequencies or power supplies of the core's PU, DTU,
and LM can be independently controlled, the FVC can vary their frequencies and
power supplies individually. For example, the FVC can stop the frequency of the PU
and run the frequencies of the DTU and LM when the core is executing only data
transfers. The on-chip shared memory (CSM) is a medium-sized on-chip memory
that is commonly used by cores. Each core is connected to the on-chip interconnect,
which may be several types of buses or crossbar switches. The chip is also con-
nected to the off-chip main memory, which has a large capacity but high latency.
Figure 2.1 illustrates a typical model of a heterogeneous multicore architecture.
A number of variations based on this architecture model are possible. Several varia-
tions of an LM structure are shown in Fig. 2.2 . Case (a) is a hierarchical structure
where the LM has two levels. LM 1 is a first-level, small-size, low-latency local
memory. LM 2 is a second-level, medium-sized, not-so-low-latency local memory.
For example, the latency from the PU to LM 1 is one processor cycle, and the latency
to LM 2 is a few processor cycles. Case (b) is a Harvard type. The LM is divided into
an LM i that stores instructions and an LM d that stores data. The PU has an indepen-
dent access path to each LM. This structure allows parallel accesses to instructions
and data and enhances processing performance. Case (c) is a combination of (a) and
(b). The LM i and LM d are first-level local memories for instructions and data,
respectively. LM 2 is a second-level local memory that stores both instructions and
data. In each case, each LM is mapped on a different address area; that is, the PU
accesses each LM with different addresses.