Hardware Reference
In-Depth Information
Chapter 6
Application Programs and Systems
6.1
AAC Encoding
This section describes the evaluation of a heterogeneous multicore architecture
consisting of a widely used advanced audio codec (AAC) [
1
] audio encoder imple-
mented on a fabricated chip. The AAC encoder is supported for audio playback by
various embedded systems. The processing scheme on the heterogeneous multi-
core architecture with support of hierarchical memories and data transfer units was
newly investigated, and the execution time and power consumption of the encoding
were measured.
6.1.1
Target System
The evaluated chip is equipped with two homogeneous CPU cores and two accel-
erators (FE-GA) [
2
] , which are described in Sect. 3.2 . Figures
6.1
and
6.2
show a
block diagram and micrograph of the chip, respectively [
3,
4
] . The chip has two
SH-4A (SH) cores capable of multicore functions such as cache snooping, a 128-
KB on-chip shared memory (CSM), a DMAC, and two FE-GAs. The SH cores have
several types of local memories and a data transfer unit (DTU). The local memories
include a 128-KB users' RAM (URAM) as a distributed shared memory, a 16-KB
operand local RAM (OLRAM) as a local data memory, and an 8-KB instruction
local RAM (ILRAM) as a local program memory. The FE-GAs also have a 40-KB
local memory (4 KB × 10 banks) that can be accessed from its internal load/store
cells as well as other processor cores. All the memories are distributed shared types,
which means they are address-mapped globally.
The SH cores are also equipped with an instruction cache and a coherent data
cache corresponding to ILRAM and OLRAM, respectively. In our use model, the data
cache is normally utilized for non-real-time applications. In contrast, the OLRAM
is used for real-time applications because data placement on the OLRAM can be
Search WWH ::
Custom Search