Application Programs and Systems - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 177

Fig. 6.1 Block diagram
of evaluated chip

CPU#0 CPU#1

SH4A
core

SH4A
core

LRAM
8+16 KB

LRAM
8+16 KB

Cache Cache

CSM
128 KB

URAM
128 KB

URAM
128 KB

DMAC

DTU DTU

STB

FE-GA#0
LM
40 KB

FE-GA#1
LM
40 KB

Memory
controller ALU

array

ALU
array

Chip

LRAM, URAM Local Memories
DTU

Data Transfer Unit

Off-chip CSM
(SDRAM)
128 MB

CSM Centralized Shared Memory

DMAC Direct Memory Access Controller

STB Split-Transaction Bus

Fig. 6.2 Micrograph
of evaluated chip

managed by software in advance of program execution. In the evaluation, an instruc-
tion cache was used instead of ILRAM. A data cache was also utilized. The array data
for the encoding program, such as the input audio-frame data and intermediately gen-
erated data, are placed on the URAM. There are certain amounts of these data, and
because they are frequently accessed by processors, their placement in a local memory
improves the performance very effectively. Otherwise, small amounts of data, such as
scholar variables, are placed in an off-chip memory (SDRAM) and cached in the data
cache. Table 6.1 lists the specifications for the evaluated chip. It is fabricated using
90-nm 8-layer CMOS technology. The operational clock frequency for CPU cores is
600 MHz and that for FE-GAs and the interconnection network is 300 MHz with the
power supplied at 1.0 V.