Software Environments - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 173

area. For DBSC-PPC, the initiators, which are two CPU cores and nine initiator
modules, access two dedicated RAM areas and a shared RAM area; therefore, this
subblock needs 11 entries for the dedicated RAM areas and 11 entries for the
shared RAM area.

5.2.5.3 PPC Error Handling

When these conditions are not satisfied, the PPC judges the access to have been
inauthentic and rejects it. The PPC then sends an error response to the internal system
bus instead of passing the access request to the target module. The PPC also gener-
ates an access-violation interrupt signal, which is transmitted to the INTC.
The interrupt controller (INTC) prioritizes interrupt sources and controls the
flow of interrupt requests to the CPU. The INTC has registers for prioritizing each
interrupt, and it processes interrupt requests following the priority order set in
these registers by the program. Most of these registers are system registers, so they
cannot be physically partitioned. Therefore, we assumed that the real-time domain
would be more reliable than the IT domain, so we decided that CPU #0, which
houses the real-time domain, should be allowed to access the INTC registers and
that the IT domain should send requests to the real-time domain for operation on
the registers.
When the INTC receives an access-violation interrupt signal, the execution
jumps to the start address of the PPC error-handling routine. Each PPC subblock has
registers that determine the access-violation interrupt signal's behavior and hold the
information on rejected access requests. Based on this information, the PPC error-
handling routine classifies the access violation's seriousness and decides whether
the system should be rebooted.

5.2.6 Evaluation

We implemented the embedded multicore processors, “RP-1,” using 90-nm CMOS
process technology with typical-case design methodology for an experimental chip
operating at a 600-MHz clock frequency. Designing and implementing the PPC is
so simple that its design impact was negligible in terms of chip area. In addition, we
did not find any critical path due to PPC in the timing analysis of the chip's
development.
To evaluate the performance overhead of PPC-based domain partitioning, we used
the LMBench [ 19 ] benchmark program and compared bare Linux with Linux on
top of a PPC error handler, run on the multicore processor. In this evaluation,
we implemented the PPC error handler as an interrupt/exception service routine that
handled the access-violation error and PPC-related system calls. So that we did not
have to modify Linux, we implemented the PPC handler like a hypervisor outside of
the operating system. Therefore, the PPC error handler checked whether the event