Background - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 6

Sequence Manager

Local Memory

Arithmetic array
(24+8 cells)
MLT
MLT
MLT
MLT
MLT
MLT
MLT
MLT

LS LRAM

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

LS
LS
LS
LS
LS
LS
LS
LS
LS

LRAM
LRAM
LRAM
LRAM
LRAM
LRAM
LRAM
LRAM
LRAM

Crossbar Switch

(10 cells) (10 banks)

Configuration Manager

ALU: 16-bit ALU cell, MUL: 16-bit Multiplier. cell
LS: Load/store cell, LRAM: Local RAM bank (4KB, 2-Port)

Fig. 1.8 Dynamic recon fi gurable processor core

but high power/area efficiency. The DSP is for signal processing applications,
and the media processor is for effectively processing various media data such as
audio and video. There are also special-purpose processor cores that are suitable
for arithmetic-intensive applications. These include the dynamically reconfigurable
core and highly SIMD (single instruction multiple data)-type core.
Figure 1.8 depicts an example of a dynamically reconfigurable processor core
[ 25 ], which is described in Sect. 3.2 in detail. It includes an arithmetic array consist-
ing of 24 ALU cells and 8 multiply cells, each of which executes a 16-bit arithmetic
operation. The array is connected to ten load/store cells with dual-ported local
memories via a crossbar switch. The core can achieve highly arithmetic-level paral-
lelism using the two-dimensional array. When an algorithm such as an FFT or FIR
filter is executed in the core, the configurations of the cells and their connections are
determined, and the data in the local RAMs are processed very quickly according to
the algorithm.
Figure 1.9 is an example of a highly SIMD-type processor core [ 26 ] , which is
described in Sect. 3.3 in detail. The core has 2,048 processing elements, each of
which includes two 2-bit full adders and some logic circuits. The processing ele-
ments are directly connected to two data register arrays, which are composed of
single-port SRAM cells. The processor core can execute arithmetic-intensive appli-
cations such as image and signal processing by operating 2,048 processing elements
in the SIMD manner.
The hardware accelerator is a core that has been developed for a dedicated appli-
cation. To achieve high power and area efficiency, the internal architecture of the