Chip Implementations - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 139

NMI
Request

Non-maskable
Interrupt (MNI)
Control

External Maskable
Interrupt Control

External
Interrupt
Request

Interrupt
Mask
Control

Interrupt
Distribution
Control

CPU
Core

CPU
Core i/f

x8 x8

x8

On-chip
Peripheral
Interrupt
Request

x8

Inter-core
Interrupt Control
IPI
reg.

On-chip Peripheral
Interrupt Control

#0 #1 #2 #3
#4 #5 #6 #7

INTC

Fig. 4.17 Block diagram of interrupt controller (INTC)

4.3.4 Interrupt Handling for Multicore

In a multicore system, multiple cores can handle interrupts, so a mechanism is nec-
essary to select the core that handles the interrupt while taking overhead reduction
into consideration. We have added an autorotating interrupt distribution scheme to
processor cores for this purpose, and the processing time in the Linux kernel was
reduced by 21% when SPLASH-2 was executed.
The RP-2 integrates a lot of peripherals and has to handle interrupt requests from
the peripherals and processor cores. Figure 4.17 illustrates a block diagram of the
interrupt controller (INTC). The INTC handles maskable/non-maskable interrupts,
on-chip peripheral interrupts, and inter-core interrupts. A request is received by the
corresponding control block, masked at the interrupt mask control block for each core,
distributed by the interrupt distribution control block, and output by the CPU core
interface for each core. An inter-core interrupt is handled by the inter-core interrupt
control block via the CPU core interface.
The interrupts have fixed and dynamic distribution modes. In the fixed distribution
mode, the interrupt request is distributed to the specific core configured by setting up
an interrupt mask register. The RP-2 has two dynamic distribution modes. In the con-
ventional dynamic distribution mode, the interrupt request is distributed simultane-
ously to all the cores and will be served by the first acknowledging one. All the cores
jump to an interrupt handling routine, check the interrupt acknowledgment register
(INTACK) in the INTC, and determine whether they should process the interrupt or
return from the handler routine. The first acknowledging core reads the INTACK
value “1” and processes the interrupt handling. The INTC clears the INTACK value
to “0” and invalidates the interrupt request. Then the other cores read “0” and return
to their tasks. This mode is best in terms of response time because the earliest respond-
ing core serves the interrupt request. However, the other cores consume redundant
operation time in the interrupt handling routine and context save/restore. The system
must pay for the overhead of the redundant time multiplied by the number of cores.