Hardware Reference
In-Depth Information
Fig. 4.18
Chip micrograph of
RP-2
The RP-2 has an autorotating dynamic distribution mode to reduce the overhead.
In this mode, the INTC asserts an interrupt request to one core for some cycles
specified by the software, which are at most 24 cycles. Then the other cores need not
consume the redundant interrupt handling time. This mode is best in terms of com-
puting throughput and can keep the worst response time of the conventional mode,
which is important in order to guarantee the response time. The average number of
clock cycles for an evaluated task is 73,028 cycles in the newly added mode, which
is 1,900 cycles fewer on average than that in the conventional mode.
In the multicore system, each core needs to interrupt other cores, and an inter-
processor interrupt (IPI) is supported by the RP-2. There are eight IPI registers in
the IPI control block for eight cores. Each core can generate an interrupt to other
cores by writing to its IPI register in the INTC. Each IPI register consists of eight
fields corresponding to the target cores.
4.3.5
Chip Integration and Evaluation
The RP-2 was fabricated using the same 90-nm CMOS process as that for the RP-1.
Figure 4.18 is the chip micrograph of the RP-2. It achieved a total of 8,640 MIPS at
600 MHz by the eight SH-X3 cores measured with the Dhrystone 2.1 benchmark
and consumed 2.8 W at 1.0 V including leakage power.
The fabricated RP-2 chip was evaluated using the SPLASH-2 benchmarks on an
SMP Linux operating system. Figure 4.19 plots the RP-2 execution time on one
cluster based on the number of POSIX threads. The processing time was reduced to
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