Hardware Reference
In-Depth Information
Chapter 4
Chip Implementations
Three prototype multicore chips, RP-1, RP-2, and RP-X, were implemented with
the highly efficient cores described in Chap. 3. The details of the chips are described
in this chapter. The multicore architecture makes it possible to enhance the perfor-
mance while maintaining the efficiency, but not to enhance the efficiency. Therefore,
a multicore with inefficient cores is still inefficient, and the highly efficient cores are
the key components to realize a high-performance and highly efficient SoC.
However, the multicore requires different technologies from that of a single core to
maximize its capabilities. The prototype chips are useful for researching and devel-
oping such technologies and have been utilized for developing and evaluating soft-
ware environments, application programs, and systems (see Chaps. 5 and 6 ).
4.1
Multicore SoC with Highly Ef fi cient Cores
A multicore system on a chip (SoC) is one of the most promising approaches to
achieve high performance. Formerly, frequency scaling was the best approach.
However, the scaling has hit the power wall, and frequency enhancement is slowing
down. Further, the performance of a single processor core is proportional to the
square root of its area, known as Pollack's rule [
1
], and the power is roughly propor-
tional to the area. Therefore, lower performance processors can achieve higher
power efficiency. As a result, we should make use of the multicore SoC with rela-
tively low-performance processors, which can achieve high power efficiency.
The power wall is not a problem only for high-end server systems. Embedded
systems also face this problem [
2
] . Figure
4.1
roughly illustrates the power budgets
of chips for various application categories. The horizontal and vertical axes repre-
sent performance measured using Dhrystone GIPS (DGIPS) and efficiency
(DGIPS/W) in logarithmic scale, respectively. The oblique lines represent constant
power (W) lines and constant product lines of the power performance ratio and the
power (DGIPS
2
/W). The product roughly indicates the attained degree of the design.
There is a trade-off relationship between the power efficiency and the performance.
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