Processor Cores - Heterogeneous Multicore Processor Technologies for Embedded Systems - page 106

a

9

8

y = 1.5871x + 0.0045

7

6

5

4

3

2

1

0

0 1 2 3 4 5 6

Original stream bit-rate (Mbps)

CABAC

b

9

y = 1.4946x + 0.0093

8

7

6

5

4

3

2

1

0

0 1 2 3 4 5 6

Original stream bit-rate (Mbps)

CAVLC

Fig. 3.79 Bit rate increase of the intermediate stream. ( a ) CABAC and ( b ) CAVLC

Table 3.19 Bandwidths used in video processing unit
DMA

Bandwidth MByte/s Note

Reference image (read) 180-806 1,920 × 1,088 × 30 × 1.5 × 2~

Reference image (write) 90 1,920 × 1,088 × 30 × 1.5

Parameters of macroblock 45 Motion vector, etc.

Steam (read) 5 40 Mbps

Intermediate stream (read + write) 16 Stream × 1.6 × 2 ch

rightward of the macroblock pipeline. This bidirectional SBUS efficiently enables
high throughput. Data are transferred by simply being shifted through shift register
slot (SRS) along the SBUS. Each SRS is assigned identification data (ID). Target
IDs are shifted along the SBUS with address, data, and enable signals, and an indi-
vidual module takes the data set into local memory when the target ID matches its
own ID, at which point the flow of that data set is terminated (not transferred to the
next module). Since there is a path traveling through the modules in sequence in
each direction, this bus architecture does not require arbitration. When the destina-
tion is not the next module to the left or right, the latency is simply proportional to