Hardware Reference
In-Depth Information
(4)
SPP or HWC
Pipeline stage (PS
n
)
Global
DMAC
SD
RAM
SPP/HWC
(PS
n-1
)
SPP/HWC
(PS
n+1
)
Counter-
clockwise
(2)
(1)
(3)
(0)
Decoder
Clockwise
Shift register
Shift register slot (SRS)
(0) DMA read
a
b
c
d
(1) PS n-1
a
b
c
d
(2) PS n
a
b
c
d
(3) PS n+1
(4) DMA write
a
b
c
d
a
b
c
d
Fig. 3.80
Shift-register-based bus network and depiction of how it works in macroblock-level
pipeline processing
the number of stages from the source module to the destination module. For a video
coding process, however, the major form of data transfer will be to the next stages
of the macroblock pipeline. Transactions between individual modules and the line
memory (L-MEM) constitute the only exception, but we avoid this problem by
scheduling this in a time slot taking up the first few tens of clock cycles before the
processing of each macroblock begins. This keeps the latency of the SBUS from
affecting the performance of the codec. The SBUS architecture provides an easy
way to connect an additional image processing unit for larger screens or a higher
frame rate without having to increase bandwidth, as would be required with a
conventional bus. The SBUS thus provides excellent video-size scalability.
The two image processing units work cooperatively as two macroblock-based
pipelines. Processing proceeds as shown in Fig.
3.81
. Most state-of-the-art video-
coding standards, including H.264, utilize context correlation between adjacent
macroblocks. For example, macroblock X is coded by using the context information
from macroblocks A, B, C, or D in Fig.
3.81
. We can take advantage of this charac-
teristic in the sophisticated dual macroblock-pipeline architecture. The delay and
parallelization for the two image processing units (IPU #0, #1) that handle the
respective pipelines are controlled accordingly. As shown in Fig.
3.82
, context
information processed by IPU #1 is directly transferred to IPU #0, and context
information from IPU #0 is transferred to L-MEM. The two macroblock lines share
L-MEM. This halves the requirement for L-MEM to store context information.
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