Hardware Reference
In-Depth Information
15. R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S.-T. Cheng,
S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. Ranjan, S. Sarwary, T. Shiple,
G. Swamy, T. Villa, VIS. in Proceedings of the Conference on Formal Methods in Computer-
Aided Design , eds. by M. Srivas, A. Camilleri. volume 1166 of LNCS , pp. 248-256. (Springer,
Berlin, 1996)
16. R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S.-T. Cheng,
S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. Ranjan, S. Sarwary, T. Shiple,
G. Swamy, T. Villa, VIS: A System for Verification and Synthesis. in Proceedings of the
Conference on Computer-Aided Verification , eds. by R. Alur, T. Henzinger. volume 1102 of
LNCS , pp. 332-334. (Springer, Berlin, 1996)
17. R. Brayton, F. Somenzi, An exact minimizer for Boolean relations. in The Proceedings of the
International Conference on Computer-Aided Design , pp. 316-319, Nov 1989
18. J. Brzozowski, Minimization by reversal is not new. Bull. Eur. Assoc. Theor. Comput. Sci.
37 , 130 (1989)
19. J.R. B uchi, The collected works of J. Richard B uchi . (Springer, Berlin, 1990)
20. J.R. B uchi, L.H. Landweber, Solving sequential conditions by finite state strategies. Trans.
Am. Math. Soc. 138 , 295-311 (1969)
21. S. Buffalov, K. El-Fakih, N. Yevtushenko, G.V. Bochmann, Progressive solutions to a parallel
automata equation. in Proceedings of the IFIP 23rd International Conference on Formal
Techniques for Networked and Distributed Systems (FORTE 2003) , volume 2767 of LNCS ,
pp. 367-382. (Springer, Berlin, 2003)
22. J.R. Burch, D. Dill, E. Wolf, G. DeMicheli, Modelling hierarchical combinational circuits. in
The Proceedings of the International Conference on Computer-Aided Design , pp. 612-617,
Nov. 1993
23. V. Bushkov, Deriving supervisors for non-terminal systems by solving equations over omega-
languages. Master's thesis, Tomsk State University, Russia, 2010. (In Russian, Original title:
Sintes compensatorov dlia sistem s neterminalnim povedeniem na osnove rescenia uravnenia
dlia omega-iazikov)
24. V. Bushkov, N. Yevtushenko, Solving parallel equations over !-languages. in Prikladnaya
Diskretnaya Matematika (Discrete Applied Mathematics), N. 2 , 117-123 (2010) (In Russian)
25. C. C. Cassandras, S. Lafortune, Introduction to Discrete Event Systems . (Kluwer, Dordrecht,
1999)
26. A.R. Cavalli, D. Lee, C. Rinderknecht, F. Zaidi, Hit-or-jump: An algorithm for embedded
testing with applications to IN services. in FORTE , pp. 41-56 (1999)
27. E. Cerny, Controllability and fault observability in modular combinational circuits. IEEE
Trans. Comput. C-27 (10), 896-903 (1978)
28. E. Cerny, Verification of I/O trace set inclusion for a class of non-deterministic finite
state machines. in The Proceedings of the International Conference on Computer Design ,
pp. 526-530, Oct. 1992
29. E. Cerny, M. Marin, An approach to unified methodology of combinational switching circuits.
IEEE Trans. Comput. C-26 (8), 745-756 (1977)
30. P. Chauhan, E. Clarke, S. Jha, J. Kukula, T. Shiple, H. Veith, D. Wang, Non-linear
quantification scheduling in image computation. in The Proceedings of the International
Conference on Computer-Aided Design , pp. 293-298, Nov. 2001
31. A. Church, Logic, arithmetic and automata. in Proceedings of the International Congress of
Mathematicians , pp. 21-35 (1963)
32. M. Damiani, The state reduction of nondeterministic finite-state machines. IEEE Trans.
Comput. Aided Des. 16 (11), 1278-1291 (1997)
33. C. Demetrescu, I. Finocchi, Combinatorial algorithms for feedback problems in directed
graphs. Inf. Process. Lett. 86 (3), 129-136 (2003)
34. S. Devadas, Optimizing interacting finite state machines using sequential don't cares. IEEE
Trans. Comput. Aided Des. 10 (12), 1473-1484 (1991)
35. D. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits .
(MIT, Cambridge, 1989)
Search WWH ::




Custom Search