Digital Signal Processing Reference
In-Depth Information
v(1)
XOR
u
v(2)
A
B
v(3)
FIGURE 10.43.
A (3,1,2) convolutional encoder.
Gaussian noise (AWGN) is generated and added to the modulated output. The
signal that is corrupted by the additive noise is fed to the channel decoder. Both the
encoder and decoder outputs are displayed within CCS. The variance of AWGN is
varied, and the decoder's performance is observed.
(3,1,2) Convolutional Encoder
Convolutional coding provides error correction capability by adding redundancy
bits to the information bits. The convolutional encoding is usually implemented by
the shift register method and associated combinatorial logic that performs modulo-
two addition, an XOR operation. A block diagram of the implemented (3,1,2) con-
volutional encoder is shown in Figure 10.43, where
u
is the input,
v
(1),
v
(2),
v
(3) are
the outputs, and
A
,
B
are the shift registers. The outputs are,
()
=
()
=≈
()
=≈≈
v
1
2
3
u
v
ub
v
ua
b
where,
a
and
b
are the contents of the shift registers A and B, respectively. Initially
the contents of the shift registers are 0s. The shift registers go through four differ-
ent states, depending upon the input (0 or 1) received. Once all the input bits are
processed, the contents of the shift registers are again reset to zero by feeding two
0s (since we have two shift registers) at the input.
State Diagram
The basic state diagram of the encoder is shown in Figure 10.44, where
S
0
,
S
1
,
S
2
,
and
S
3
represent the different states of the shift registers. Furthermore,
m/xyz
indicates that on receiving an input bit
m
, the output of the encoder is
xyz
; that is,
if
u
z
for that particular state of shift registers A
and B. The arrows indicate the state changes on receiving the inputs.
=
m
=>
v
(1)
=
x
,
v
(2)
=
y
,
v
(3)
=
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