DSP Instruction Set Simulation - Signal Processing Systems - page 947

machines that control which functions need to be invoked. This is particularly
important for handling various hazards, interlocks, and stalls that may emerge
during the simulation. These techniques allow a very detailed simulation of the
dynamic behavior of a processor; the generated simulators thus achieve very
accurate results. However, simulation speed is usually not satisfactory.
Retargetable simulators based on compiled simulation and dynamic binary
translation can be used to circumvent the problem of unsatisfactory speed. In a
similar manner to the interpreter approach, simulation functions are generated.
However, these functions do not emulate the behavior of the instruction itself but
instead generate code that is later executed. In the case of static compiled simulation,
code fragments of a high-level language, such as C, are emitted by these functions
that precisely emulate the instruction's behavior. In the case of dynamic compilation
and binary translation, machine code fragments or fragments of an intermediate
representation that can be compiled to machine code are emitted.
Integrating retargetable simulation engines with other simulation tools and
external components is often a major problem. This is in part caused by the very
nature of these engines. The generic architecture independent parts are incomplete
without the generated portions of the simulator. Extending them is complex and
often impossible without considering the processor model. The generated portions
on the other hand can not be modified directly without losing the advantage of
retargetability. Leveraging existing general-purpose modeling frameworks such as
SystemC [ 68 ] is a viable option that allows interfacing with a large number of
existing models that come with these frameworks. Some processor description
languages take this idea even a step further and do not supply a specialized
language to specify the instruction semantics. Instead, a general purpose modeling
language can be used, allowing the processor model to directly interact with external
components and models.

8 Related Work on Simulation Approaches

Interpretive Simulation

Klint describes the classic implementation of an ISA interpreter [ 37 ] . In 1990
James Larus made SPIM available [ 41 ] . SPIM is an interpretive simulator for the
MIPS architecture which is commonly used for teaching. SPIM takes assembly
language programs as input which are stored in an intermediate representation.
Magnusson shows how instruction cache simulation and execution profiling can be
done efficiently with a threaded-code interpreter [ 42 ] . Processors with out-of-order
execution usually are simulated using interpretive simulation since static modeling
of the dynamic behavior of the processor is nearly impossible. A famous interpretive
simulator for such kind of processors is SimpleScalar [ 3 ] .