Digital Signal Processing Reference
In-Depth Information
Fig. 10
During design space exploration the processor model, specified using a processor
description language, is iteratively adopted in order to achieve the best possible performance,
power, and area trade-off for a given DSP application
7.2
Retargetable Simulation
A key component that comes with virtually every processor description language
is a simulation framework that can be customized and adapted quickly and
easily to a new architecture model. This is usually achieved by generating the
processor specific portions of the simulator, e.g., a software instruction decoder and
appropriate simulation functions that model the behavior of individual instruction.
The simulation techniques employed by these
retargetable
simulation engines do
not differ from those found in hand-coded simulators, and range from simple
functional interpreters and highly sophisticated binary translators to highly precise
event-driven simulators. However, these engines potentially have to cope with a
large range of different architectures, making optimizations found in hand-written
simulators impossible in these engines for the sake of generality. It is thus not
uncommon for retargetable simulation engines to restrict the range of supported
architectures to certain architecture styles. In-order pipelined architectures, for
example, are typically well supported, while less attention is typically paid to
dynamic features of modern superscalar processors. It is important to note that
the execution model of the processor description language and the techniques used
to implement the execution model within the retargetable simulation framework
may impact the accuracy of the simulation results. Designers thus need to evaluate
whether the processor description language and its accompanying tools are suited
for the particular task at hand.
As with hand-coded frameworks, the simplest form of retargetable simulation is
interpretation. The semantic information that is available in the processor models
is grouped into simple simulation functions that are invoked from within the
interpreter loop. Each function performs an atomic simulation step that is indivisible
for external observers during simulation. In the case of functional simulation, a
single function is generated that captures the behavior of the instruction completely.
For transaction-based or even cycle-accurate simulation, multiple simulation func-
tions are emitted. The simple interpreter loop is usually also extended using state
