DSP Instruction Set Simulation - Signal Processing Systems - page 944

7 Generation of Instruction Set Simulators

Designing and developing an instruction set simulator for a new architecture or
processor design is a cumbersome and error-prone task. Especially during the
early stages of the design process, the instruction set and its implementation
may change frequently and thus complicate the task of simulator development.
Processor description languages [ 35 , 46 ] provide a promising approach in which
the specification of the instruction set and implementation details of a new design
are specified using a formal language. These languages provide helpful abstractions,
leading to processor models that are easy to maintain and extend, and thus reduce
development time and cost. Furthermore, these languages allow for design space
exploration , a technique for exploring different processor designs in order to find
the best solution for a particular task. The resulting application-specific instruction
processors (ASIP) combine superior performance and reduced power consumption
while still providing a certain degree of flexibility in comparison to pure hardware
solutions.

7.1 Processor Description Languages

The development of a specialized DSP architecture is typically constrained by
development cost, time to market, and the production cost per unit. Efficient and
accurate simulation tools play a central role in exploring and evaluating design
alternatives. In addition, these tools allow software development to start during the
early stages of the design process. This not only leads to a shorter development
cycle, but also lets developers collect data and perform various measurements
that are crucial for tuning the design to the requirements of the application
domain in question. However, developing a new instruction set simulator, or even
customizing existing tools, is an error-prone and time-consuming task. Extensible
and maintainable models of the processor design are thus desperately needed.
Processor description languages and related tools provide a promising solution
to this problem. In recent years, these languages have evolved from being mere
research projects into products that are actively used and successfully adopted by
leading companies in order to develop and design highly specialized and tuned
architectures [ 30 ] . A processor model typically consists of several layers that
include information on the hardware organization, the instruction set, instruction
semantics and timing. Meta information such as assembly syntax, application
binary interface (ABI) conventions, etc., can be specified in most languages.
Structuring the models, for example by instruction classes, enables code reuse
across different instructions and leads to concise and compact models. In this way,
adding new instructions or adapting existing instructions is often only a matter of
a few lines of code. Processor description languages, sometimes also referred to as