Digital Signal Processing Reference
In-Depth Information
Fig. 9
Simulation can be performed in part using software techniques and hardware components.
An efficient partitioning of such a simulation system is to perform the complex timing emulation
within an FPGA, while a purely functional simulation is executed on the host computer
operate in parallel: the functional model and the timing model. In the case of
trace-driven
simulation, sometimes also referred to as
functional-first
simulation,
the simulation process is controlled by the functional model. On the other hand,
in
timing-directed
simulation, also called
timing-first
simulation, the timing model
controls and drives progress. In the former case, the functional model executes the
program without considering dynamic effects, such as variable latency instructions,
interlocking, branch prediction, or cache and memory delays. If, at some point,
the timing model detects a mismatch between the instruction stream executed by
the functional model and the instructions executed on a real system, e.g., due to
a mispredicted branch, the simulation has to be reverted and restarted in order
to correct the mismatch. In trace-driven systems, the timing model has control
and triggers the execution of the functional model at the appropriate times. Both
approaches share the advantage that the functional model can be implemented using
software techniques, and are thus more flexible and easier to extend than hardware
models. However, there is no reason why the functional part could not execute
Another approach is to divide the simulation tasks between hardware and soft-
ware depending on execution frequency and implementation complexity. Certain
simulation tasks are selectively promoted to hardware if they dominate the perfor-
mance of the system and if their implementation in hardware is cheap in terms of
implementation effort and hardware resources.
