Digital Signal Processing Reference
In-Depth Information
43. Kim, M., Hwang, I., Chae, S.I.: A fast VLSI architecture for full-search variable block
size motion estimation in MPEG-4 AVC/H.264. In: Proc. Asia and South Pacific Design
Automation Conference, pp. 631-634 (2005)
44. Koester, S.J., Young, A.M., Yu, R.R., Purushothaman, S., Chen, K.N., La Tulipe, D.C., Rana,
N., Shi, L., Wordeman, M.R., Sprogis, E.J.: Wafer-level 3D integration technology. IBM
Journal of Research and Development 52 (6), 583-597 (2008)
45. Lapsley, P., Bier, J., Shoham, A., Lee, E.A.: DSP Processor Fundamentals: Architectures and
Features. IEEE Press (1997)
46. Lee, C., Potkonjak, M., Mangione-Smith, W.: MediaBench: a tool for evaluating and syn-
thesizing multimedia and communications systems. In: Proc. of IEEE/ACM International
Symposium on Microarchitecture, pp. 330-335 (1997)
47. Lee, S., Chen, K.N., Lu, J.Q.: Wafer-to-wafer alignment for three-dimensional integration: A
review. Journal of Microelectromechanical Systems 20 (4), 885-898 (2011)
48. Li, R., Zeng, B., Liou, M.L.: A new three-step search algorithm for block motion estimation.
IEEE Trans. on Circuits and Systems for Video Technology 4 , 438-442 (Aug.)
49. Liu, C.C., Ganusov, I., Burtscher, M., Tiwari, S.: Bridging the Processor-Memory Performance
Gap with 3D IC Technology. IEEE Design and Test of Computers 22 , 556?64 (2005)
50. Loh, G.: 3D-stacked memory architecture for multi-core processors. In: Proceedings of the
35th ACM/IEEE Intl. Conf. on Computer Architecture (2008)
51. Loh, G., Xie, Y., Black, B.: Processor Design in 3D Die-Stacking Technologies. IEEE Micro
27 , 31-48 (2007)
52. Lu, J.Q.: 3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems. Pro-
ceedings of the IEEE 97 , 18-30 (2009)
53. Lu, J.Q., Cale, T., Gutmann, R.: Wafer-level three-dimensional hyper-integration technology
using dielectric adhesive wafer bonding. Materials for Information Technology: Devices,
Interconnects and Packaging (Eds. E. Zschech, C. Whelan, T. Mikolajick) pp. 386-397
(Springer-Verlag (London) Ltd, August 2005)
54. Matick, R., Schuster, S.: Logic-based eDRAM: Origins and rationale for use. IBM J. Res. &
Dev. 49 , 145-165 (2005)
55. M.Facchini, T.Carlson, A.Vignon, M.Palkovic, F.Catthoor, W.Dehaene, L.Benini, P.Marchal:
System-level power/performance evaluation of 3d stacked drams for mobile applications. In:
Proc. of Design, Automation & Test in Europe Conference & Exhibition, pp. 923-928 (2009)
56. Moor, P.D., Ruythooren, W., Soussan, P., Swinnen, B., Baert, K., Hoof, C.V., Beyne, E.: Recent
advances in 3d integration at imec. Enabling Technologies for 3-D Integration (edited by C.A.
Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)
57. Morrow, P., Black, B., Kobrinsky, M., Muthukumar, S., Nelson, D., Park, C.M., Webb, C.:
Design and fabrication of 3d microprocessors. Enabling Technologies for 3-D Integration
(edited by C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)
58. Nain, R., Chrzanowska-Jeske, M.: Fast Placement-Aware 3-D Floorplanning Using Vertical
Constraints on Sequence Pairs. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems 19 (9), 1667-1680 (2011)
59. Panda, P.R., Catthoor, F., Dutt, N.D., Danckaert, K., Brockmeyer, E., Kulkarni, C., Kjeldsberg,
P.G.: Data and memory optimization techniques for embedded systems. ACM Transactions on
Design Automation of Electronic Systems 6 , 149-206 (2001)
60. Po, L.M., Ma, W.C.: A novel four-step search algorithm for fast block motion estimation. IEEE
Trans. on Circuits and Systems for Video Technology 6 , 313-317 (1996)
61. Pozder, S., Chatterjee, R., Jain, A., Huang, Z., Jones, R., Acosta, E.: Progress of 3D Integration
Technologies and 3D Interconnects. In: Proc. of IEEE International Interconnect Technology
Conference, pp. 213-215 (2007)
62. Pozder, S., Jones, R., Adams, V., Li, H.F., Canonico, M., Zollner, S., Lee, S., Gutmann, R.,
Lu, J.Q.: Exploration of the scaling limits of 3d integration. Enabling Technologies for 3-D
Integration (edited by C.A. Bower, P.E. Garrou, P. Ramm, and K. Takahashi) (2006)
63. Rickert, P., Krenik, W.: Cell phone integration: SiP, SoC, and PoP. IEEE Design & Test of
Computers 23 , 188-195 (2006)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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