General-Purpose DSP Processors - Signal Processing Systems - page 784

consists 200-300 DSP cores interconnected with mesh type of interconnection. The
cores are 16-bit 3-way VLIW processors [ 10 ] . Although in many of these multicore
systems, there are shared memory resources, the programming model is based on
message passing.
Yet another type of multicore organisation can be found from Sandbridge
SB3500 chip [ 33 , 36 ] , which is heterogeneous system consisting of a general-
purpose ARM processor and three multithreaded DSP cores. The processors use
token triggering threading, thus threads are guaranteed to have a fixed number
of cycles between issuing consecutive instructions. Each core has four hardware
threads, which can execute 16-wide vector operations. the multithreading hides
latencies in unconditional branches, interrupts, and memory accesses.

8 Conclusions

The DSP processor architectures have evolved over the time. Early DSP processors
were programmed manually with assembly language and high performance was
obtained with specialized function units operating in parallel. This implied non-
orthogonal complex instruction set computer (CISC) type of instruction sets that
are poor targets for compilers. Although reduced instruction set computer (RISC)
and superscalar architectures have gained popularity in general-purpose computing,
they have not been the mainstream in DSP processors. This is partly due to the
fact that often DSP applications set hard real-time requirements indicating that the
execution time of the software implementation should be deterministic. Typically
the features used in superscalar processors introduce dynamic run-time behavior
resulting in non-deterministic execution times.
Various methods to exploit parallelism has been used to improve the perfor-
mance. Conventional DSP processor architectures have been enhanced with mul-
tiple MAC units, e.g., TMS320C55x, ADSP-BF5xx, or additional co-processors.
Multiple function units are exploited with SIMD extensions, e.g., in SIMD mode
in ADSP-21xxx, second data path executes the same operations as the instruction
defines for the first data path but for a different register file. Multi-issue processors
in form of VLIW machines have gained popularity in DSP applications.

9 Further Reading

Other chapters in the handbook cover topics related to DSP processors; Franke [ 11 ]
discusses C compilers and code optimisation for DSP processors, Kessler [ 25 ]
covers topics on compiling for VLIW DSPs, and Carro and Rutzig [ 9 ] introduces
multicore system-on-chips. There are many textbooks discussing DSP processors
and interested readers are advised to consider the following: [ 1 , 21 , 27 - 29 ] . In
addition, Berkeley Design Technologies [ 7 ] carries out independent benchmarking