Digital Signal Processing Reference
In-Depth Information
X0 (24)
24
24
X1 (24)
Y0 (24)
Y1 (24)
24
24
MULTIPLIER (24*24->48)
48
pipeline register
48
BIT FIELD UNIT & SHIFTER
56
56
SHIFTER
ALU/LIMITER
56
56
A (56)
B (56)
56
56
24
24
SHIFTER/LIMITER
Fig. 2
Principal data path of Freescale DSP56300
L1 Data Cache Controller
DA1 addr
DA2 addr
LD/ST data
LD/ST data
.L1
.S1
.M1
.D1
.D2
.M2
.S2
.L2
Odd Register File A1, A3, A5, …, A31
Odd Register File B1, B3, B5, …, B31
Even Register File A0, A2, A4, …, A30
Even Register File B0, B2, B4, …, B30
Fig. 3
Principal data path of TI TMS320C64x
