Digital Signal Processing Reference
In-Depth Information
DATA BUS (16)
T-REGISTER (16)
MULTIPLIER (16*16->32)
P-REGISTER (32)
SHIFTER
SHIFTER
ALU (32)
ACCUMULATOR (32)
DATA MEMORY (16-bit)
SHIFTER
Fig. 1
Principal data path of TI TS320C25
×
multiplications, dual 16
16 multiplications, and Galois field multiplication. These
two units support also dual 16
×
×
8 MAC operations. Freescale
MSC8156 contains six SC3850 DSP cores and the data path of each core contains
four ALUs, which can perform dual 16
16 and quad 8
×
16 MAC operations. The ALUs support
also complex-valued multiplication of operands with 16-bit real and imaginary
3.1.2
Registers
Early DSP processors were load-store architectures where operands in memory have
to be moved to specific operand registers before the operand can be transferred to
a functional unit. In a similar fashion, results from functional units were stored to
specific registers or accumulators. In early DSP processor, the number of general-
purpose registers was small indicating need to store intermediate results to memory.
This represents clearly a performance bottleneck. Higher performance can be
