FPGA-Based DSP - Signal Processing Systems - page 715

S

Nios II Processor

Hardware Accelerator

M M M M

Avalon
Switch

S S S S

Peripherals

Instruction
Memory

Data
Memory

Data
Memory

Fig. 15 Nios processor and subsystem architecture [ 3 ]

4.2.2 Nios-Centric Reconfigurable Processor Design

The Altera Nios II softcore processor exists as part of an extended subsystem
architecture, which is shown in Fig. 15 . As this shows, custom hardware accelerators
may be integrated into the Nios memory subsystem using the Altera Avalon Switch
Fabric [ 2 ] .
Altera also offer a simple mechanism for quickly developing new co-processors
which fit into this subsystem architecture. Altera's Nios II C2H Compiler [ 3 ] allows
a user to describe the functionality of the system in Nios II compatible C code,
and offload critical parts of the code to a co-processor, which is then automatically
created and inserted into the subsystem of Fig. 15 . A simple set of rules, outlined in
Tab le 4 , are used to convert C commands to a hardware architecture. This one-to-
one mapping style makes the method of constructing the co-processor architecture
explicit to the designer, allowing them to manipulate the C program to optimise it.
The C2H Compiler also provides rudimentary architectural optimisations; in par-
ticular automatically pipelining and scheduling loops and automatically removing
Avalon master ports when several connect to the same memory block, merging the
references and scheduling the accesses internally.