FPGA-Based DSP - Signal Processing Systems - page 714

a

Memory Management Unit

CacheS I/F

CacheM I/F

CacheM I/F

ALU

CacheS I/F

Program
Counter

Shift

Special
Purpose
Registers

PLB I/F

Bus
Interface

Barrel Shift

Bus
Interface

OPB I/F

Multiplier

PLB I/F

Divider

LMB I/F

OPB I/F

Instruction
Buffer

FPU

Instruction
Decode

LMB I/F

MFSL I/F

32 x 32 Register
File

SFSL I/F

b

Microblaze
Instruction Decoder

ALU R-file DBus

SR-
file

VR-
file

VR-
file

VR-
file

ALU ALU ALU

SIMD Coprocessor

Microblaze reconfigurable processing architecture. ( a ) Microblaze ® Fig. 14 Softcore Processor

Architecture [ 41 ] , ( b ) FSL-based Microblaze ® Coprocessing [ 7 ]

Of particular significance is the configurable use of Fast Simplex Links (FSLs).
A Microblaze ® can host up to 16 FSLs, which are dedicated, point-to-point
unidirectional data streaming interfaces, offering a low-latency interface directly
into the processor pipeline for external co-processors. A simple schematic of how
such a co-processor interfaces to the Microblaze using FSLs is given in Fig. 14 b .