Digital Signal Processing Reference
In-Depth Information
ASIP requirement specification
Early manual partition according to source code profiling and product requirements
Implement the function as an instruction
Instruction set
specification
Processor architecture
specification
Implement the function as a subroutine
Microarchitecture design
Assembly instruction set simulator
Move a subroutine to an instruction
Benchmarking of
instruction set
Design for HW
acceleration
Change an instruction to a subroutine
Application SW implementation
Processor HW implementation
ASIP Integration, final function verification and performance validation
Fig. 14
Hardware/software co-design for an ASIP
means to design software subroutine of the function. After source code profiling, an
instruction set architecture can be proposed. Further HW/SW co-design of ASIP in
Fig.
14
is to modify the proposal by trading off HW/SW partition through all design
steps of an ASIP.
An ASIP assembly instruction set should be efficient enough to offer perfor-
mance for the most frequently appearing functions and be general enough to cover
all functions in the specified application domains. When the performance is not
enough, the most used (kernel) subroutines or algorithms should be hardware-
accelerated. Those subroutines or algorithms that are seldom used should be
implemented as SW subroutines. Performance and coverage can be fulfilled by
carefully trading off the HW/SW partitioning.
However, functional coverage evaluation is not easy. So far, there is no better way
than running real applications. The cost is high and it takes a long time. HW/SW
4.5
Design Automation of an Instruction Set Architecture
Researchers are working towards multi-objective-oriented evaluation tools to com-
pare and select among different solutions. Many researchers also work on iden-
tification of functions to be accelerated and propose instructions for functional
acceleration. Also many researchers are working on ASIP synthesis.
