Application Specific Instruction Set DSP Processors - Signal Processing Systems - page 675

Fig. 13 Hardware/software
co-design flow

System design inputs

Early HW/SW partition

SW specification HW specification

Programming HW modeling

SW simulation HW simulation

SW implementation HW implementation

Integration and tests

From HW design perspective, functions assigned to HW team are allocated
to HW modules. Modules could be either processors or functional circuits. The
behaviors of programmable HW modules can be described by assembly language
simulator. The behaviors of non-programmable HW modules can be described by
HW description languages. A function implemented in programmable hardware will
be an assembly language instruction. Functions implemented in non-programmable
hardware will be hardware modules or parts of a hardware module.
Finally, the implemented SW and HW is integrated. The implemented binary
code of the assembly programs will be executed on the implemented HW. The
design flow in Fig. 12 is principally correct because it follows the golden rule of
design: divide-and-conquer. However, when designing a high quality embedded
system, we actually do not know how to make a correct or optimized early partition.
In other words, the early partition may not be good enough without iterative
optimizations through the design.
To optimize a design, we need to interactively move functions between SW and
HW design teams during the embedded system design. Under such a challenge,
“HW/SW co-design” appeared in the early 1990s.
The HW/SW co-design flow is depicted in Fig. 13 . Following the figure, the
idea of the new design flow is to optimize the partition of HW and SW functions
cooperatively at each design step during the embedded system design. HW/SW
co-design is to trade-off function partition and implementation between SW and
HW through embedded system design. Eventually, the results will be optimized
following certain goals. Re-partition is not difficult. The difficulty is the fast and
quantitative modeling for functional verification as well as performance and cost
estimation of the new design after each re-partition. Fast processor prototyping is
therefore a challenging research topic [ 4 ] .
The implementation of an algorithm level function in ASIP HW is to design
accelerated instructions for the specific function. Implementing a function in SW