Digital Signal Processing Reference
In-Depth Information
After determining the functional coverage requirement of the ASIP, source code
of applications will be collected and source code profiling will be conducted in
order to further understand applications. The inputs of the source code profiling are
the collected source code and application scenarios. The outputs of the source code
profiling are the results of the code analysis including the estimated complexity,
computing cost, data access cost, and memory cost. During source code profiling,
the early partitioning of hardware and software can be proposed.
Hardware/software partitioning for an ASIP is the trade-off of function allocation
to hardware or to software tasks. Implementing a task in software means to write
a subroutine of the task in assembly language or in C. Implementing a task in
hardware means to implement functions on an accelerated instruction or several
accelerated instructions. ASIP instruction set design can be guided by the “10-90%
code locality rule”, which has been used as the rule of thumb in ASIP design in
The locality rule means that 10% of the instructions run at 90% time and 90%
of the instructions appear only 10% of the execution time. In other words, the
essential of ASIP design is to find the best instruction set architecture optimized
for accelerating the 10% most frequently used instructions and to specify the rest of
90% instructions to fulfil functional coverage.
Based on the exposed 90-10% code locality, hardware requirements can be
specified and a specific architecture of the ASIP can be proposed accordingly.
ASIP architecture proposal could be based on a selected available architecture
with modifications. If flexibility is an essential requirement, selecting an available
architecture, such as VLIW architecture might be preferred. A typical case is to
select VLIW or master-slave SIMD architecture for a multi-mode image and video
signal processing.
An ASIP architecture could also be a dataflow architecture generated from the
dataflow analysis during source code profiling. If the requirements on performance
and computing latency are exceptionally tough, normal available architectures
may not offer sufficient performance. A dataflow architecture might thus be a
good choice. For example a dataflow architecture is suitable for a radio baseband
processor in an advanced radio base station.
Following a proposed architecture, an assembly instruction set is proposed and its
instruction set simulator is implemented for benchmarking. Cost trade-off analysis
of the instruction set and the hardware architecture is performed. The inputs of the
assembly instruction set design include the architecture proposal, profiling results
of the source code, and the 90-10% code locality analysis. If a good reference
instruction set can be found from a previous product or from a third party, the
design of ASIP will be faster. The output of the assembly instruction set design
is the assembly instruction set manual.
Instruction set design consists of the functional specification of instructions,
allocation of functions to hardware, and coding of the instruction set. The coding
of the instruction set includes the design of the assembly syntax and the design of
the binary machine codes. Finally binary codes are executed by the instruction set
simulator for benchmarking. The performance of the instruction set and the usage
of each instruction is exposed for further optimization.
