Coarse-Grained Reconfigurable Array Architectures - Signal Processing Systems - page 540

Coarse-Grained Reconfigurable Array
Architectures

Bjorn De Sutter, Praveen Raghavan, and Andy Lambrechts

Abstract Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate
the same inner loops that benefit from the high ILP support in VLIW architectures.
Unlike VLIWs, CGRAs are designed to execute only the loops, which they can
hence do more efficiently. This chapter discusses the basic principles of CGRAs and
the wide range of design options available to a CGRA designer, covering a large
number of existing CGRA designs. The impact of different options on flexibility,
performance, and power-efficiency is discussed, as well as the need for compiler
support. The ADRES CGRA design template is studied in more detail as a use case
to illustrate the need for design space exploration, for compiler support and for the
manual fine-tuning of source code.

1 Application Domain

Many embedded applications require high throughput, meaning that a large number
of computations needs to be performed every second. At the same time, the power
consumption of battery-operated devices needs to be minimized to increase their
autonomy. In general, the performance obtained on a programmable processor for
a certain application can be defined as the reciprocal of the application execution
time. Considering that most programs consist of a series P of consecutive phases
with different characteristics, performance can be defined in terms of the operating
frequencies f p , the instructions executed per cycle IPC p and the instruction counts

B. De Sutter ( )
Ghent University, Sint-Pietersnieuwstraat 41, 9000 Gent, Belgium
e-mail: [e-mail]
P. Raghavan ￿ A. Lambrechts
IMEC, Kapeldreef 75, 3001 Heverlee, Belgium
e-mail: [e-mail] ; [e-mail]