Digital Signal Processing Reference
In-Depth Information
Multiprocessing Modeling
High-End single-Processor Modeling
Application “A”
Application “A”
T1
T2
I
1
I
2
I
3
I
4
I
5
d
I
0
I
1
S1
?
I
6
I
7
I
9
T3
T4
d
I
2
1
7
1
3
1
4
1
5
1
6
2
1
S2
S3
T5
T6
T7
?
1
8
1
9
2
0
I
3
I
3
I
4
I
5
I
6
d
Parallel Code (a)
Parallel Code (d)
Sequential Code ( )
Sequential Code (?)
Fig. 5
Modeling of the (
a
) multiprocessor system and the (
b
) high-end single-processor
many simple and homogeneous cores without any capability to explore instruction
level parallelism (ILP) to elucidate the advantages of Thread Level Parallelism
(TLP) exploitation. We also compare its Execution Time (ET) to a high-end single
processor
SHE
(
Single High-End
) model, which is able to exploit only ILP available
in applications.
We have considered different amounts of fine- (instruction) and coarse- (thread)
level parallelism available in the application code to investigate the performance
potentials of the both aforementioned architectures.
Considering a part of a given application code, we classify it in four different
ways:
α
- the instructions that can be executed in parallel in a single processor;
β
- the instructions that cannot be executed in parallel in a single processor;
δ
- the amount of instructions that can be distributed among the processors of the
multiprocessor environment.
γ
- the amount of instructions that cannot be split, and therefore must be executed
in one of the processors among those in the multiprocessor environment.
Figure
5
exemplify how the previously stated classification, considering a certain
application “A”, would be applied. In the example shown in this figure, when
application code can be parallelized at some degree (i.e. divided in threads) and
executed on different cores at the same time, so
δ
=
γ
=
0.3. On the other
hand, when the very same application “A” is executed on the high-end single-
in parallel at some degree, so
0.7 and
α
=
β
=
0.64 and
0.36.
