Digital Signal Processing Reference
In-Depth Information
8-tap FIR
8x8 DCT
Maximum Value
64-pt FFT
20
18
16
14
12
10
8
6
4
2
0
1
2
5
8
10
13
15
20
23
25
Number of DSP processors
Fig. 4
applications are deployed. Hence, the multiprocessing system appears, also in the
DSP domain, as a solution to supply the high performance requirements. The major
advantage of multiprocessing elements on the DSP domain is the inherent Thread-
Figure
4
illustrates the speedup provided by a multiprocessing system for DSP
applications. The speedup for the Maximum Value application increases almost
linearly with the number of processor. The eight-tap FIR and 64-pt FFT also show
optimistic speedups when the number of processing elements increases. On the other
hand, the 8
×
8 Discrete Cosine Transform provides the smallest speedup among the
application workload. Clearly, this application is a good example for Amdahl's law,
demonstrating that multiprocessing systems can fail to accelerate applications that
have a meaningful sequential part.
The rest of this chapter is divided into five major sections. First, a more detailed
analytical modeling is provided to show the actual design space of multiprocessing
devices in the DSP field. Next, an MPSoC hardware taxonomy is presented, aiming
to explain the different architectures and applicability domain. MPSoC systems
are classified taking into account two points of view: architecture and employed
organization. A dedicated section demonstrates some successful MPSoC designs.
A section discusses open problems in MPSoC design, covering from software
development, communication infrastructure. Finally, future challenges like how can
one overcome Amdahl's law limitations are covered.
2
Analytical Model
In this sub-section, we try to figure out the potential of single parallelism exploita-
tion by modeling a multiprocessing architecture (
MP-MultiProcessor
) composed of
