Architectures for Stereo Vision - Signal Processing Systems - page 499

4 Summary

There has been and continues to be tremendous research in the field of computer
vision, both on the algorithmic side and on the hardware side. Nowadays, many
implementations for GPUs, FPGAs, ASICs, DSPs, and ASIPs are available. These
cover a huge variety of algorithms and design aspects (e.g. algorithmic performance
vs. silicon area). The two example implementations on the GPU and the FPGA for
semi-global matching based disparity estimation show, that it is possible to realize
high quality stereo correspondance search in real-time. The GPU implementation
enables SGM processing with eight paths but without left/right check with more
than 62 fps of images with a resolution of 640

480 and 128 disparity levels on
Nvidia Fermi architecture GPUs. The VLSI architecture is scalable and allows exact
adaptation to the particular application. For the same image resolution frame rates
of 1

×

7 fps to 319 fps are achieved at a operating frequency of 133 MHz. Which of
both architectures is the more suitable solution depends on the external parameters.

.

5 Further Reading

A detailed algorithmic overview is provided in the textbook [ 83 ] and the surveys
[ 29 , 81 , 85 ] . Epipolar geometry and rectification is covered in [ 34 , 103 ] . The OpenCV
library provides many functions for stereo processing [ 11 ] . For multi-view stereo
and 3D reconstruction [ 83 ] is a good starting point.
Dedicated image processing architectures including rectification and many more
are covered in [ 3 ] and RTL hardware design in [ 15 ] . Various kinds of computer
architectures including GPUs are found in the newest edition of [ 35 ] .

References

1. Ambrosch, K., Kubinger, W.: Accurate hardware-based stereo vision. Computer Vision and
Image Understanding, Elsevier 114 , 1303-1316 (2010)
2. Arias-Estrada, M., Xicotencatl, J., Brebner, G., Woods, R.: Multiple stereo matching using
an extended architecture. Proc. Field-Programmable Logic and Applications 2147 , 203-212
(2001)
3. Bailey, D.G.: Design for embedded image processing on FPGAs. John Wiley & Sons,
Singapore (2011)
4. Banz, C., Blume, H., Pirsch, P.: Real-time semi-global matching disparity estimation on the
GPU. Proc. IEEE Intl. Conf. Computer Vision Workshops pp. 514-521 (2011)
5. Banz, C., Blume, H., Pirsch, P.: Evaluation of penalty functions for SGM cost aggregation.
Intl. Archives of Photogrammetry and Remote Sensing (2012)
6. Banz, C., Dolar, C., Cholewa, F., Blume, H.: Instruction set extension for high throughput
disparity estimation in stereo image processing. Proc. IEEE Intl. Conf. Architectures and
Processors Application Specific Systems pp. 169-175 (2011)