Architectures for Stereo Vision - Signal Processing Systems - page 498

Fig. 18 Hardware setup of the stereo vision system with the system board and the stereo camera
rig. On the right is the input image of lab scene and the computed raw disparity map before false
color visualization and sending to display is conducted

is considerably different from a typical AT-diagram, which would be inadequate for
this comparison as it would not reflect the throughput constraint.
For a small number of parallel disparity levels, increasing disparity level
parallelism is very efficient since it has a significantly smaller influence on the total
resource usage than increasing row level parallelism. However, row parallelism is
the key concept for stream-based processing and crucial for a high base performance
but increases linearly with the number of rows. The full potential of the parallelism
approaches is exploited when using a combination of both, i.e. by using a small
number of parallel rows and additionally introducing disparity level parallelism
up to the configuration that does not yet require additional memory resources. For
example, starting from the ( p r = 1)-configuration a performance increase

of approximately factor two can be achieved by doubling the number of either
parallel rows or disparity levels. Increasing disparity level parallelism does not
increase BRAM requirements (not shown, see [ 8 ] ) and results in a LUT saving of
factor 1.8. The major benefit of increasing disparity level parallelism is that local
memory requirements remain constant for both, path costs buffers and input/output
buffers.
A stereo vision system covering the entire stereo vision process including image
acquisition, noise reduction, rectification, disparity estimation, post processing,
and visualization has been integrated into a single FPGA. The system has been
integrated on a custom build hardware platform show in Fig. 18 . This work shows
that it is possible to implement an algorithmically extremely high performing
disparity matching algorithm in an FPGA with true real-time performance. More
details on the implementation can be found in [ 8 ] .

10 , d m =