Digital Signal Processing Reference
In-Depth Information
a
x
vco
(
t
)
(
t
)
LPF
VCO
linear
phase-detector
1
(
t
)
in
k
VCO
s
s
k
PD
1
+
LPF
(
t
)
vco
b
BB
phase-detector
(
t
)
f
ast path
q
R
(
t
)
in
k
VCO
s
1
(t)
sC
vco
slow path
Fig. 7
Phase-locked loop (PLL): (
a
) linear, and (
b
) binary or bang-bang PLL
receiver. The CRU generates symbol timing information and the receiver clock from
the received analog signal in the presence of dispersion, noise, and input jitter.
A PLL forms the basis of the operation of a CRU. A PLL can be viewed as
an extremely narrowband filter with its passband centered at a frequency equal to
the symbol-rate. A traditional PLL is referred to as a
linear PLL
because the PLL
functionality in the phase domain can be easily described using linear feedback
compute the instantaneous phase-error
Δφ
(
)
(
)
t
between the input phase
φ
t
and
in
(
)
the clock phase
. The phase error is integrated using a low-pass filter (LPF)
whose output is used to control the input voltage, and hence the frequency, of a
voltage-controlled oscillator (VCO). At high-speeds, the linear PD is unable to
generate narrow pulses that represent small phase-errors. Thus, most high-speed
BB-PLL is best understood by considering a 1st order loop, which is obtained by
3-level, phase-error
φ
t
vco
(
)
is generated using a BB phase-detector (BB-PD). The
BB-PD ensures that the VCO frequency switches between two extremes
f
nom
Δφ
t
q
±
f
bb
,
also called the
lock range
,where
f
nom
is the nominal data frequency, which is made
equal to the symbol-rate, and
f
bb
is the frequency step. Thus, unlike in a linear
PLL, the VCO in a BB-PLL operates at two discrete frequencies separated by
2
f
bb
. A 1st-order BB-PLL locks as long as the average data frequency lies in the
lock range. Otherwise, the VCO starts to hunt for the right frequency and in the
process generates hunting jitter, whose amplitude is proportional to the lock range.
