Mapping Decidable Signal Processing Graphs into FPGA Implementations - Signal Processing Systems - page 1353

from the SFG description; a key step is to iterate around this loop to optimize
the performance typically minimizing area requirements for the throughput rate
required. As will be demonstrated in the chapter, the generation of the circuit
architecture can be complicated when the SFG representation involves feedback
loops.
Given the make-up of FPGA architectures with either separate multiplier and
adder circuits or in the case of more recent FPGA architectures, dedicated DSP
blocks with fixed wordlength representations and also distributed memory, the
design focus used in this chapter, is to optimize the circuit architecture in terms of
these building blocks. It should be noted that some synthesis tools now offer some
level of pipelining and retiming as an option but these features have limited impact
as shown by the synthesis results given.

1.1 Chapter Breakdown

The chapter is organized as follows. A brief review of FPGA hardware platforms
is given in Sect. 2 concentrating on the features most relevant to DSP in recent and
powerful FPGA families from Xilinx and Altera namely the Virtex ® and Stratix ®
families. The focus of the section is to highlight the key features of the families and
not provide a detailed description of the technologies. Section 3 highlights the key
steps in create FPGA circuit architectures for various speed and area requirements,
covering retiming and delay scaling . Optimizing the circuit architecture to meet
certain performance criteria is achieved by applying folding and unfolding either
to increase speed or if the speed requirement has been met, to achieve better
overall performance by reducing area requirements; finally, the LMS filter is used to
demonstrate the various optimization and covers various FPGA design trade-offs;
this is covered in Sect. 4 . The chapter concludes by looking at how some of core
features are exposed to the system designer and also how some of the techniques
can be used to reduce dynamic power consumption.

2 FPGA Hardware Platforms

Historically, FPGAs were viewed as a glue logic component where the design
focus was on maximizing LUT utilization and minimizing programmable routing
to provide interconnectivity at the lowest possible delay. With regard to structure,
FPGAs are categorized by the following programmable components although the
granularity of some of blocks may have changed over the years:

￿ Programmable logic units that can be programmed to realize different digital

functions.

￿ Programmable interconnect that allow different blocks to be connected together.

￿ Programmable I/O pins.