Mapping Decidable Signal Processing Graphs into FPGA Implementations - Signal Processing Systems - page 1352

Fig. 1 SFG to FPGA circuit architecture design flow

With non-recurrent engineering (NRE) costs and increasing design challenges
for sub-65 nm CMOS technology, programmability is becoming increasingly impor-
tant. The existence of programmable platforms such as DSP processors allow users
to develop software descriptions and then use commercially available compilers and
assemblers to create the resulting designs. This approach has numerous advantages
including software portability, ease of modification and product migration, and
reduced design time compared to ASIC or FPGA solutions. FPGAs also offer
programmability but unlike processors, involve the creation of the architecture
which is typically a complex design process. However, this offers the key advantage
to achieve very high performance but with the use of prefabricated technology; this
avoids the non-recurrent engineering (NRE) costs associated with implementing
designs using ASIC technology.
The main issue therefore, is to map the DSP functionality efficiently onto the
hardware effectively creating a circuit architecture which best matches the system
requirements. This is ideally achieved by making modifications to the signal flow
graph (SFG) representation of the algorithm such as those highlighted in chapters
[ 3 , 12 ] , so that an efficient circuit architecture can be produced. The basic process
for realizing a circuit architecture from a SFG description is given in Fig. 1 . The
initial stage involves investigating performance using suitable design software e.g.
Simulink ® or LabVIEW, to determine issues such as suitable wordlengths, etc.;
the next stage is to determine performance in terms of the sampling rate required,
latency, etc. and then use these parameters to generate the circuit architecture