Digital Signal Processing Reference
In-Depth Information
Fig. 4
Fixed-point multiplication
a
b
Fig. 5
Floating-point to fixed-point conversion of a recursive filter. (
a
) Floating-point filter,
(
b
) Fixed-point filter
and 1. The output signal is also known to be between
3 and 5.3. The output signal
range is obtained from floating-point simulation results. The coefficient is 0.9, and is
unsigned. Hence, the range of the multiplied signal,
z
−
5
.
[
n
]
, will be 4.77 (
=
0
.
9
∗
5
.
3).
From the given range information, we can assign the IWL's of 0 for
x
[
n
]
,3for
y
[
n
]
,
3for
z
and 0 for the coefficient. The coefficient
a
is coded as “58982,” which
corresponds to the unsigned number 0
[
n
]
2
16
. Since the multiplication of
y
.
9
×
[
n
]
and
a
is conducted between signed and unsigned numbers, the IWL of
z
is 3, which is
I
y
+
I
a
. If the coefficient
a
is coded with the two's complement format, the IWL of
z
[
n
]
would be 4 due to the extra sign generated in the multiplication process. Since
the precision of the hardware multiplier is 16-bit, only the upper 16 bits, including
the sign bit, of
y
[
n
]
is used for the multiplication. The quantizer (Q) in this figure
takes the upper 16 bits among 32 bits of
y
[
n
]
[
n
]
. Since the difference between
I
x
and
I
z
is 3,
x
is scaled down or arithmetic shift-righted by 3 bits, as the hardware in
There are a few different fixed-point implementations. One example is a fixed-
point implementation without needing shift operations. Note that no shift operation
is needed when adding or subtracting two fixed-point data with the same integer
word-length. In this case, the IWL of 3 is assigned to the input
x
[
n
]
[
n
]
, even though
