Optimization of Number Representations - Signal Processing Systems - page 1283

Fig. 3 Fixed-point addition with different IWL's

Tabl e 1 Fixed-point arithmetic rules

Fixed-point

Floating-
point

I x > I y , I z I y > I x , I z I z > I x , I y Result IWL

Assignment x = y x = y x = y - I x

( I x − I y ) ( I y − I x )

Addition/
Subtraction

z = x + yz =( x +( y z =(( x ( I y − z =( x max ( I x , I y , I z )

( I x − I y ))) I x ))+ y ) ( I z − I x ))+

( I x − I z ) ( I y − I z ) ( y

( I z − I y ))

Multiplication x ∗ y mulh ( x , y ) I x + I y + 1or

I x + I y

z : a variable storing the result

are shown in Table 1 , where Ix and Iy are the IWL's of two input operands x and y ,
respectively, and Iz is that of the result, z .
In fixed-point multiplication, the word-length of the product is equal to the
sum of two input word-lengths. In two's complement multiplication, two identical
sign bits are generated except for the case that both input data correspond to the
negative minimum, “100 0.” Ignoring this case, the IWL of the two's complement

multiplied result becomes Ix

···

1. Figure 4 shows the multiplied result of two
8-bit fixed-point numbers. By assuming the IWL of 5, we can obtain the interpreted
value of 2.25.

+ Iy +

2.3 Fixed-Point Conversion Examples

To illustrate the fixed-point conversion process, a floating-point version of the
recursive filter shown in Fig. 5 a is transformed to a fixed-point hardware system.
Assume that the input signal has the range of 1, which implies that it is between − 1