Digital Signal Processing Reference
In-Depth Information
Software Compilation Techniques for MPSoCs
Rainer Leupers, Weihua Sheng, and Jeronimo Castrillon
Abstract
The increasing demands such as high-performance and energy-efficiency
for future embedded systems result in the emerging of heterogeneous Multipro-
cessor System-on-Chip (MPSoC) architectures. To fully enable the power of those
architectures, new tools are needed to take care of the increasing complexity of
the software to achieve high productivity. An
MPSoC compiler
is the tool-chain
to tackle the problems of expressing parallelism in applications' modeling/pro-
gramming, mapping/scheduling and generating the software to distribute on an
MPSoC platform for efficient usage, for a given (pre-)verified MPSoC platform.
This chapter talks about the various aspects of MPSoC compilers for heterogeneous
MPSoC architectures, using a comparison to the well-established uni-processor C
compiler technology. After a brief introduction to MPSoC and MPSoC compilers,
the important ingredients of the compilation process, such as programming models,
granularity and partitioning, platform description, mapping/scheduling and code-
generation, are explained in detail. As the topic is relatively young, a number of
case studies from academia and industry are selected to illustrate the concepts at the
end of this chapter.
1
Introduction
1.1
MPSoCs and MPSoC Compilers
Lately it has become clear that Multiprocessor System-on-Chip (MPSoC) is the
most promising way to keep on exploiting the high level of integration provided
R. Leupers (
) W. Sheng J. Castrillon
Institute for Software for Systems on Silicon, RWTH Aachen University, SSS-611910,
Templergraben 55, 52056 Aachen, Germany
