Digital Signal Processing Reference
In-Depth Information
floating-point unit
32
32-bit
processor
32
system
services
32
link
services
link
interface
32
timers
32
32
4 kbytes
on-chip
RAM
link
interface
32
32
link
interface
link
interface
32
external
memory
interface
32
32
event
Fig. 14
INMOS T805 floating-point processor
(
http://www.classiccmp.org/transputer
)
the networking circuitry finished its reads or writes. Other processes running on the
transputer would then be given that processing time. These unique properties allow
multiple Transputer chips to be configured easily into various topologies such as
linear or mesh array, or trees to support parallel processing.
Depicted in Fig.
14
is a chip layout picture and a floor plan of Transputer T805.
It has a 32-bit architecture running at 25 MHz clock frequency. It has an IEEE 754
64-bit on-chip floating-point unit, 4 Kbytes on-chip static RAM, and may connect
to 4 GB directly addressable external memory (no virtual memory) at 33 Mbytes/s
sustained data rate. It uses a 5 MHz clock input and runs on a single 5 V power
supply.
Transputers were intended to be programmed using the Occam programming
language, based on the CSP process calculus. Occam supported concurrency and
channel-based inter-process or inter-processor communication as a fundamental part
of the language. With the parallelism and communications built into the chip and the
language interacting with it directly, writing code for things like device controllers
became a triviality. Implementations of more mainstream programming languages,
such as C, FORTRAN, Ada and Pascal, were also later released by both INMOS
and third-party vendors.
5.4
TMS 32040
developed in early 1990. The ***'320C40 has six on-chip communication ports
