Digital Signal Processing Reference
In-Depth Information
global data
...
I/O
and
buffer
...
to / from
system
memory
...
Zone 0
memory
Zone 1
memory
Zone 31
memory
...
Fig. 13
The Matrix Processor Zone architecture of SAXPY Matrix-1 computer
capabilities, and a 4K-word local memory implemented as a two-way interleaved
zone buffer. These components operate at a clock frequency of 16 MHz. With 32
zones, the maximum computing power would approach 960 MFLOP.
The Matrix-1 employs an application programming interface (API) approach to
interface with the host processor. The user program will be written in C or Fortran
and makes calls to the matrix processor subroutines. Experienced programmers may
also write their own matrix processor subroutines or directly engage assembly level
programming of the matrix processors.
5.3
Transputer
by Inmos Ltd. in mid-1980s to support parallel processing. The name was selected
to indicate the role the individual Transputers would play: numbers of them would
be used as basic building blocks, just as transistors in integrated circuits.
A most distinct feature of a Transputer chip is that there are four serial links
to communicate with up to four other Transputers simultaneously each at 5, 10 or
20 Mbit/s. The circuitry to drive the links is all on the Transputer chip and only
two wires are needed to connect two Transputers together. The communication
links between processors operate concurrently with the processing unit and can
transfer data simultaneously on all links without the intervention of the CPU.
Supporting the links was additional circuitry that handled scheduling of the traffic
over them. Processes waiting on communications would automatically pause while
